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Re: Driver for IGBT? (-ve off and +ve on from CMOS)

Subject: Re: Driver for IGBT? -ve off and +ve on from CMOS
From: Terry Given
Date: Tue, 11 Oct 2005 10:18:27 +1300
Newsgroups: sci.electronics.basics,
Ignoramus14838 wrote:
On Tue, 11 Oct 2005 09:03:50 +1300, Terry Given <[email protected]> wrote:

Ignoramus14838 wrote:

On Mon, 10 Oct 2005 11:50:18 -0700, Jamie 
<[email protected]> wrote:

Richard wrote:

I would like to drive an IGBT from a microcontroller (CMOS).
Is there a driver circuit that can outputs around  +15v (on) and a -5v (off)
for  switching frequencies around 40Khz.
I think -ve voltage supply is avaliable
What is this type of circuit called?


i really don't understand why you need that?, normally pulling the
gate low will do how ever if you insist.

I am actually playing with IGBTs. I have Toshiba-MG200Q2YS40 IGBT.
It does NOT turn off itself if I simply remove Gate/Emitter voltage.

I have to apply reverse voltage to turn it off. I actually tried it.

a decent short from gate to emitter would do it.

It would, possibly, switch itself off with a small resistor between
gate and emitter, but it is just a hypothesis of mine.


what you are loking at is a combination of things - miller effect mostly. There is a non-linear capacitance between gate and collector, call it Ccg. Whenever the collector voltage changes value (say from Vcesat to Vdc when turning off) the voltage slews at some rate, dV/dt. This causes current to flow thru Ccg, Icg = Ccg*dVce/dt. This current flows into the gate circuit, charging up Cge. If the gate driver is not very low impedance, Icg will happily charge Cge up to Vth, and beyond. when turning the IGBT on, Vce falls so Icg flows out of Cge, discharging it - IOW trying to turn it back off.

This can greatly increase switching time (and hence losses) and, if the gatedrive is bad enough, can make the device "latch" in the on-state, with Vge sitting around Vth - but you need a seriously piss-weak gate driver to do that. It can even over-voltage the gate, poke a hole thru the thin gate oxide layer, and KABOOM, one dead IGBT.

a negative gate bias means the switch-off miller current has to supply more charge to reach Vth - instead of supplying Qg = Vth*Cge, it must supply (Vth + |Vnegative|)*Cge. This allows the use of higher gate impedance circuitry. Its not just the resistance, its the inductance too. bad gate drives have high resistance and high inductance; good gate drives have low resistance and low inductance.

to give you an idea, I've worked on gatedrives for 0.5kW - 2.2kW drives that have about -3V reverse-bias, and -15V for 400kW drives (6 300A fuji IGBTs directly paralleled).

modern IGBT designs have much better packaging - far lower inductance, both Lce and Lge. with some of these IGBTs it is theoretically possible to keep the gate impedance sufficiently low that negative bias isnt necessary. Like I said, IR wrote a pretty good paper on the topic - why you dont, in theory, need -ve bias for little IGBTs.

In practice, if you screw up the gatedriver, your circuit is going to go BANG. If you really know what you are doing, and are very good at taking measurements, its fairly easy to dewsign gatedrivers and make them work. OTOH if you are not too experienced, its very easy to destroy many, many IGBTs.

Generally the gatedrive is a lot cheaper than the IGBTs, so its sensible to throw -ve bias at it. For little IGBTs, it can be as simple as a zener in series with the gate resistor, with a 100nF cap across it.

Terry, it is great that you participate in this thread and actually
have experience with power switching. I am building a DC -> AC
inverter for a TIG welder and seems like I can learn a lot from you.
This is a 200A constant current, 28 V welding current, 80 v open
circuit voltage tig welder.I have aforementioned IGBTs.

Can you give a little schematic of how go give the gates negative bias
during turn off. I definitely want to turn IGBTs off in the best
possible way. I want the simplest solution.

here's one simple solution: use an optocoupler to drive a FET driver chip, running from a +10V/-5V supply. connect the supply 0V to the IGBT emitter, +10V to the driver chip Vcc and -5V to the driver chip gnd. that way the driver chip "sees" a 15V supply, whereas the IGBT "sees" +10V and -5V.

we used to use tens of thousands of UC3842 smps chips as gate drivers. An opto drove the 3842, which ran from a 15V isolated supply. the 3842 Vref output was connected to the IGBT emitter, giving +10V/-5V gate drive. We had hefty caps from +10V to 0V to -5V. for little drives. for big drives, we used +/-15V supplies.

for really little drives (< 2kW) we used the series zener trick. get a 15V FET driver, with a 15V supply. bung a 5V zener in series with the output, with a 100nF cap across it. When the gatedrive output is high, 5V is dropped across the zener, charging the cap - the cathode end of the cap is 5V below the anode end, and the gate gets 10V.

when the gatedrive output switches to 0V, the anode end of the cap is at 0V. The cathode end of the cap is 5V more negative than the anode end, so the gate sees -5V. The 100nF cap needs to be at least 10x the gate capacitance. For larger IGBTs, 1uF would be better.

this is probably the easiest option for you, and works with *any* gate driver. Make sure you use a stompy zener though - you dont want its series impedance to be large compared to your gate resistor. Think BZT03 or suchlike.

gatedrives are tricky, and until they work you kill a lot of IGBTs. why not just buy one from Semikron.

Another question, would a resistor between gate and emitter solve ths
issue? Or is that not the case?

yes but no. You would need a seriously low valued resistor (< 10R) to even attempt to hold the IGBT off wrt Cmiller, which would quite successfully bugger up the gatedrive. not to mention the 15V^2/10R = 22W or more power dissipation when the gatedrive is ON.

thanks a lot for your time!



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