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Re: WG Item?: draft-zinin-microloop-analysis-01.txt

Subject: Re: WG Item?: draft-zinin-microloop-analysis-01.txt
From: Alia Atlas
Date: Tue, 21 Jun 2005 15:48:44 -0400

At 10:20 AM 6/16/2005, mike shand wrote:
On the complexity front, I think we can probably omit the type B
destinations (treating them as type Cs). This will give slightly worse
performance (but my simulations indicate this is quite a small
change), but will allow the convergence to be complete after 1 rather
than 2 delay cycles, and will avoid the need to change a FIB entry for
a destination twice. This is probably a tradeoff worth making (since
neither gives complete protection).

Where would you insert stopping using the LFA into a scheme without
the type B?  I agree that type B didn't appear frequently - but it's
also not clear to me that there is a large complexity associated with
implementing it.


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