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On Wed, Sep 03, 2008 at 10:04:39PM +0200, Andreas Färber wrote:
> Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with
> tcg_gen_mov_tl.
> Introduce TCG variables cpu_gpr[0..31].
>
> For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
> Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and
> helpers
> gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and
> Blue.
>
> Signed-off-by: Andreas Faerber <andreas.faerber@xxxxxx>
> ---
> target-ppc/cpu.h | 12 +-
> target-ppc/op_template.h | 85 ------
> target-ppc/translate.c | 747 +++++++++++++++++++++++
> +----------------------
> 3 files changed, 390 insertions(+), 454 deletions(-)
>
I do not feel comfortable of defining t0, t1, t2 as both 32-bit and
64-bit variables in TCG. I have already seen aliasing problems at some
point.
I have therefore applied your patch, as well as another one which
defines separate t0_64, t1_64, t2_64 registers on 32-bit targets. At the
end of the conversion to TCG, those variables will disappear anyway.
Thanks for your work.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@xxxxxxxxxx | aurelien@xxxxxxxxxxx
`- people.debian.org/~aurel32 | www.aurel32.net
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