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PERFORCE change 110486 for review

Subject: PERFORCE change 110486 for review
From: Oleksandr Tymoshenko
Date: Fri, 24 Nov 2006 17:09:07 GMT
http://perforce.freebsd.org/chv.cgi?CH=110486

Change 110486 by gonzo@gonzo_hq on 2006/11/24 17:08:31

        o Add UserIntr and UserGenException routines 
        o Handle case of userland-generated traps and interrupts
            in ExceptionVector code.

Affected files ...

.. //depot/projects/mips2/src/sys/mips/mips/exception.S#14 edit

Differences ...

==== //depot/projects/mips2/src/sys/mips/mips/exception.S#14 (text+ko) ====

@@ -23,7 +23,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#13 $
+ * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#14 $
  */
 
 /*     $NetBSD: mipsX_subr.S,v 1.19 2005/12/11 12:18:09 christos Exp $ */
@@ -199,6 +199,42 @@
        .dword  GenericException        /* Res (30) */
        .dword  VCED                    /* VCED */
 
+       ####
+       #### Here comes user exception handlers
+       ####
+       .dword  UserIntr                /* Int */
+       .dword  UserGenericException    /* TLBMod */
+       .dword  UserGenericException    /* TLBL */
+       .dword  UserGenericException    /* TLBS */
+       .dword  UserGenericException    /* AdEL */
+       .dword  UserGenericException    /* AdES */
+       .dword  UserGenericException    /* IBE */
+       .dword  UserGenericException    /* DBE */
+       .dword  UserGenericException    /* Sys */
+       .dword  UserGenericException    /* Bp */
+       .dword  UserGenericException    /* RI */
+       .dword  UserGenericException    /* CpU */
+       .dword  UserGenericException    /* Ov */
+       .dword  UserGenericException    /* Tr */
+       .dword  UserGenericException    /* VCEI */
+       .dword  UserGenericException    /* FPE */
+       .dword  UserGenericException    /* Res (16) */
+       .dword  UserGenericException    /* Res (17) */
+       .dword  UserGenericException    /* Res (18) */
+       .dword  UserGenericException    /* Res (19) */
+       .dword  UserGenericException    /* Res (20) */
+       .dword  UserGenericException    /* Res (21) */
+       .dword  UserGenericException    /* Res (22) */
+       .dword  UserGenericException    /* WATCH */
+       .dword  UserGenericException    /* Res (24) */
+       .dword  UserGenericException    /* Res (25) */
+       .dword  UserGenericException    /* Res (26) */
+       .dword  UserGenericException    /* Res (27) */
+       .dword  UserGenericException    /* Res (28) */
+       .dword  UserGenericException    /* Res (29) */
+       .dword  UserGenericException    /* Res (30) */
+       .dword  VCED                    /* VCED */
+
        .text
        .set noreorder
 
@@ -212,10 +248,14 @@
 LEAF(ExceptionVector)
        .set noat
 
-       mfc0    k0, MIPS_COP_0_CAUSE
-       and     k0, MIPS3_CR_EXC_CODE
+       mfc0    k0, MIPS_COP_0_CAUSE            ## k0 = cause
+       and     k0, MIPS3_CR_EXC_CODE           ## mask out 
        srl     k0, MIPS_CR_EXC_CODE_SHIFT
+       mfc0    k1, MIPS_COP_0_STATUS
+       and     k1, k1, MIPS_SR_KSU_USER
+       sll     k1, k1, 4
        sll     k0, 3 /* Index 64-bits. */
+       or      k0, k0, k1
        la      k1, ExceptionHandlerTable
        addu    k1, k0
        lw      k1, 0(k1)
@@ -280,7 +320,6 @@
        mtc0    zero, MIPS_COP_0_STATUS
        COP0_SYNC
        nop
-       nop
        jal     trap
        nop
 2:
@@ -317,17 +356,21 @@
 1:     .asciiz "Cache Vector"
        .text
 
+/*
+ * Handles kernel mode TLBInvalid exception for KVA
+ * All other cases are handled by GeneticException 
+ */
 LEAF(TLBInvalidVector)
        .set noat
        mfc0    k0, MIPS_COP_0_BAD_VADDR        # k0=badaddr
+       li      k1, VM_MIN_KERNEL_ADDRESS
        bgez    k0, GenericException
-       nop
+       subu    k0, k0, k1
 
        /* VPN2 = (VA >> page_shift) / 2 */
-       la      k1, VM_MIN_KERNEL_ADDRESS
-       subu    k0, k0, k1
        srl     k0, PAGE_SHIFT + 1
 
+
        /* 
         * XXXMIPS: 
         * offset == VPN2 * sizeof(pt_entry_t)  * 2
@@ -394,9 +437,7 @@
        eret
 
 tlbnotfound:
-       la      k0, panic
-       mtc0    k0, MIPS_COP_0_EXC_PC
-       la      a0, 2f
+       break
        eret
 VEND(TLBInvalidVector)
        .data
@@ -404,7 +445,7 @@
        .text
 
 /*
- * XXX kernel only.  For now that makes sense.
+ * Handle TLBMiss exception. 
  */
 LEAF(TLBMissVector)
        .set noat
@@ -412,6 +453,7 @@
        mfc0    k0, MIPS_COP_0_BAD_VADDR        # k0=badaddr
        bltz    k0, 5f                          # k0<0 -> 5f (kernel fault)
        nop
+
 6:
        /* Userland */
        lui     k1, %hi(segtab_active)  
@@ -424,6 +466,7 @@
        mfc0    k0, MIPS_COP_0_BAD_VADDR        # k0=bad address (again)
        beq     k1, zero, 7f                    # ==0 -- no page table
        srl     k0, 10                          # k0=VPN (aka va>>10)
+       nop
 
        andi    k0, k0, 0xff8                   # k0=page tab offset
        addu    k1, k1, k0                      # k1=pte address
@@ -438,13 +481,11 @@
        nop                                     # standard nop
        tlbwr                                   # write to tlb
        nop                                     # standard nop
-       nop                                     # needed by R4000/4400
-       nop                                     # needed by R4000/4400
        eret                                    # return from exception
 5:
        j       KVATLBMiss
        nop
-7:     j       GenericException
+7:     j       UserGenericException
        nop
 
 VEND(TLBMissVector)
@@ -562,6 +603,128 @@
        .set at
 END(VCEDX)
 
+/* 
+ * Handle trap from userspace (VM-related, syscall, etc..)
+ */
+NESTED(UserGenericException, TF_SIZE, ra)
+       .set noat
+       .set noreorder
+       .mask   0x80000000, -4
+       lw      k1, pcpup
+       lw      k1, PC_CURTHREAD(k1)
+       lw      k1, TD_MD_REALSTACK(k1)         # load wired region 
+       la      k0, 1f
+       j       exception_save_registers
+       nop
+1:
+       move    a0, k1                          # For following trap call
+       addu    sp, k1, -TF_SIZE                # Switch to kernel's stack
+
+       ###
+       ### Fill out trap arcguments and call it
+       ###
+       /*
+        * Call trap() with arguments:
+        * trapframe, cause, badvaddr.
+        *
+        * Cause is set up above when computing the code.
+        */
+       mfc0    a1, MIPS_COP_0_CAUSE
+       mfc0    a2, MIPS_COP_0_BAD_VADDR
+       mfc0    t0, MIPS_COP_0_STATUS
+       .set at
+       and     t0, t0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK | 
MIPS_SR_INT_IE)
+       .set noat
+
+       mtc0    t0, MIPS_COP_0_STATUS
+       COP0_SYNC
+
+       nop
+       jal     trap
+       nop
+
+
+       ###
+       ### TODO: Check pending traps here.
+       ###
+
+       /*
+        * Make sure interrupts are disabled for the purposes of
+        * having a clean go at restoring.
+        */
+       mtc0    zero, MIPS_COP_0_CAUSE
+
+       ###
+       ### Restore regiters and bail out
+       ###
+       addu    sp, sp, TF_SIZE                 ## Restore pointer to saved 
+                                               ## registers
+       move    k1, sp
+       jal     exception_restore_registers
+       nop
+       eret
+       .set at
+VEND(UserGenericException)
+       .data
+1:     .asciiz "UserGenericException"
+       .text
+
+/*
+ * Handle interrupt from userspace
+ */
+NESTED(UserIntr, TF_SIZE, ra)
+       .set noat
+       .set noreorder
+       .mask   0x80000000, -4
+       lw      k1, pcpup
+       lw      k1, PC_CURTHREAD(k1)
+       lw      k1, TD_MD_REALSTACK(k1)         # load wired region 
+       la      k0, 1f
+       j       exception_save_registers
+       nop
+1:
+       move    a0, k1                          # For following trap call
+       addu    sp, k1, -TF_SIZE                # Switch to kernel's stack
+
+       mfc0    t0, MIPS_COP_0_STATUS
+       .set at
+       and     t0, t0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK | 
MIPS_SR_INT_IE)
+       .set noat
+
+       mtc0    t0, MIPS_COP_0_STATUS
+       COP0_SYNC
+
+       nop
+       jal     cpu_intr
+       nop
+
+
+       ###
+       ### TODO: Check pending traps here.
+       ###
+
+       /*
+        * Make sure interrupts are disabled for the purposes of
+        * having a clean go at restoring.
+        */
+       mtc0    zero, MIPS_COP_0_CAUSE
+       mtc0    zero, MIPS_COP_0_STATUS
+
+       ###
+       ### Restore regiters and bail out
+       ###
+       addu    sp, sp, TF_SIZE                 ## Restore pointer to saved 
+                                               ## registers
+       move    k1, sp
+       jal     exception_restore_registers
+       nop
+       eret
+       .set at
+
+VEND(UserIntr)
+       .data
+1:     .asciiz "UserIntr"
+       .text
 
 /*
  * Restore registers from a trapframe pointed to in k1, returning to ra
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