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PERFORCE change 75261 for review

Subject: PERFORCE change 75261 for review
From: Peter Wemm
Date: Fri, 15 Apr 2005 18:18:46 GMT
http://perforce.freebsd.org/chv.cgi?CH=75261

Change 75261 by peter@peter_overcee on 2005/04/15 18:18:27

        Integ -b i386_hammer (pick up mixed_mode changes)

Affected files ...

.. //depot/projects/hammer/sys/amd64/acpica/madt.c#39 integrate
.. //depot/projects/hammer/sys/amd64/amd64/cpu_switch.S#31 integrate
.. //depot/projects/hammer/sys/amd64/amd64/genassym.c#38 integrate
.. //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#36 integrate
.. //depot/projects/hammer/sys/amd64/amd64/io_apic.c#38 integrate
.. //depot/projects/hammer/sys/amd64/amd64/local_apic.c#48 integrate
.. //depot/projects/hammer/sys/amd64/amd64/machdep.c#123 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#89 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mptable.c#40 integrate
.. //depot/projects/hammer/sys/amd64/amd64/sys_machdep.c#20 integrate
.. //depot/projects/hammer/sys/amd64/amd64/trap.c#57 integrate
.. //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#69 integrate
.. //depot/projects/hammer/sys/amd64/conf/NOTES#62 integrate
.. //depot/projects/hammer/sys/amd64/include/apicvar.h#31 integrate
.. //depot/projects/hammer/sys/amd64/include/clock.h#16 integrate
.. //depot/projects/hammer/sys/amd64/include/pc/display.h#6 integrate
.. //depot/projects/hammer/sys/amd64/include/pcb.h#22 integrate
.. //depot/projects/hammer/sys/amd64/include/pcpu.h#23 integrate
.. //depot/projects/hammer/sys/amd64/include/segments.h#19 integrate
.. //depot/projects/hammer/sys/amd64/include/sysarch.h#17 integrate
.. //depot/projects/hammer/sys/amd64/isa/clock.c#38 integrate

Differences ...

==== //depot/projects/hammer/sys/amd64/acpica/madt.c#39 (text+ko) ====

@@ -367,8 +367,6 @@
        }
                    
        /* First, we run through adding I/O APIC's. */
-       if (madt->PCATCompat && !(acpi_quirks & ACPI_Q_MADT_IRQ0))
-               ioapic_enable_mixed_mode();
        madt_walk_table(madt_parse_apics, NULL);
 
        /* Second, we run through the table tweaking interrupt sources. */

==== //depot/projects/hammer/sys/amd64/amd64/cpu_switch.S#31 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/genassym.c#38 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#36 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/io_apic.c#38 (text+ko) ====

@@ -32,7 +32,6 @@
 
 #include "opt_atpic.h"
 #include "opt_isa.h"
-#include "opt_no_mixed_mode.h"
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -62,7 +61,6 @@
 #define        VECTOR_DISABLED         255
 
 #define        DEST_NONE               -1
-#define        DEST_EXTINT             -2
 
 #define        TODO            printf("%s: not implemented!\n", __func__)
 
@@ -83,15 +81,6 @@
  * IO APIC has a contiguous chunk of the System Interrupt address space.
  */
 
-/*
- * Direct the ExtINT pin on the first I/O APIC to a logical cluster of
- * CPUs rather than a physical destination of just the BSP.
- *
- * Note: This is disabled by default as test systems seem to croak with it
- * enabled.
-#define ENABLE_EXTINT_LOGICAL_DESTINATION
- */
-
 struct ioapic_intsrc {
        struct intsrc io_intsrc;
        u_int io_intpin:8;
@@ -130,7 +119,6 @@
 static void    ioapic_resume(struct intsrc *isrc);
 static void    ioapic_program_destination(struct ioapic_intsrc *intpin);
 static void    ioapic_program_intpin(struct ioapic_intsrc *intpin);
-static void    ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
 
 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
@@ -140,13 +128,7 @@
                               ioapic_config_intr };
        
 static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
-static u_int mixed_mode_enabled, next_id, program_logical_dest;
-#if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC)
-static int mixed_mode_active = 0;
-#else
-static int mixed_mode_active = 1;
-#endif
-TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
+static u_int next_id, program_logical_dest;
 
 static __inline void
 _ioapic_eoi_source(struct intsrc *isrc)
@@ -270,12 +252,8 @@
        struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
        uint32_t low, high, value;
 
-       /*
-        * For pins routed via mixed mode or disabled, just ensure that
-        * they are masked.
-        */
-       if (intpin->io_dest == DEST_EXTINT ||
-           intpin->io_vector == VECTOR_DISABLED) {
+       /* For disabled pins, just ensure that they are masked. */
+       if (intpin->io_vector == VECTOR_DISABLED) {
                low = ioapic_read(io->io_addr,
                    IOAPIC_REDTBL_LO(intpin->io_intpin));
                if ((low & IOART_INTMASK) == IOART_INTMCLR)
@@ -346,8 +324,6 @@
 
        KASSERT(intpin->io_dest != DEST_NONE,
            ("intpin not assigned to a cluster"));
-       KASSERT(intpin->io_dest != DEST_EXTINT,
-           ("intpin routed via ExtINT"));
        if (bootverbose) {
                printf("ioapic%u: routing intpin %u (", io->io_id,
                    intpin->io_intpin);
@@ -383,8 +359,6 @@
 {
        struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
 
-       KASSERT(intpin->io_dest != DEST_EXTINT,
-           ("ExtINT pin trying to use ioapic enable_intr method"));
        if (intpin->io_dest == DEST_NONE) {
                ioapic_assign_cluster(intpin);
                lapic_enable_intr(intpin->io_vector);
@@ -465,17 +439,6 @@
 }
 
 /*
- * APIC enumerators call this function to indicate that the 8259A AT PICs
- * are available and that mixed mode can be used.
- */
-void
-ioapic_enable_mixed_mode(void)
-{
-
-       mixed_mode_enabled = 1;
-}
-
-/*
  * Allocate and return a logical cluster ID.  Note that the first time
  * this is called, it returns cluster 0.  ioapic_enable_intr() treats
  * the two cases of logical_clusters == 0 and logical_clusters == 1 the
@@ -503,11 +466,20 @@
        u_int numintr, i;
        uint32_t value;
 
+       /* Map the register window so we can access the device. */
        apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
        mtx_lock_spin(&icu_lock);
-       numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
-           MAXREDIRSHIFT) + 1;
+       value = ioapic_read(apic, IOAPIC_VER);
        mtx_unlock_spin(&icu_lock);
+
+       /* If it's version register doesn't seem to work, punt. */
+       if (value == 0xffffff) {
+               pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
+               return (NULL);
+       }
+
+       /* Determine the number of vectors and set the APIC ID. */
+       numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
        io = malloc(sizeof(struct ioapic) +
            numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
        io->io_pic = ioapic_template;
@@ -547,12 +519,11 @@
                intpin->io_vector = intbase + i;
 
                /*
-                * Assume that pin 0 on the first I/O APIC is an ExtINT pin
-                * if mixed mode is enabled and an ISA interrupt if not.
+                * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
                 * Assume that pins 1-15 are ISA interrupts and that all
                 * other pins are PCI interrupts.
                 */
-               if (intpin->io_vector == 0 && mixed_mode_enabled)
+               if (intpin->io_vector == 0)
                        ioapic_set_extint(io, i);
                else if (intpin->io_vector < IOAPIC_ISA_INTS) {
                        intpin->io_bus = APIC_BUS_ISA;
@@ -710,12 +681,7 @@
                return (EINVAL);
        io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
        io->io_pins[pin].io_vector = VECTOR_EXTINT;
-
-       /* Enable this pin if mixed mode is available and active. */
-       if (mixed_mode_enabled && mixed_mode_active)
-               io->io_pins[pin].io_masked = 0;
-       else
-               io->io_pins[pin].io_masked = 1;
+       io->io_pins[pin].io_masked = 1;
        io->io_pins[pin].io_edgetrigger = 1;
        io->io_pins[pin].io_activehi = 1;
        if (bootverbose)
@@ -790,15 +756,7 @@
                ioapic_program_intpin(pin);
                if (pin->io_vector >= NUM_IO_INTS)
                        continue;
-               /*
-                * Route IRQ0 via the 8259A using mixed mode if mixed mode
-                * is available and turned on.
-                */
-               if (pin->io_vector == 0 && mixed_mode_active &&
-                   mixed_mode_enabled)
-                       ioapic_setup_mixed_mode(pin);
-               else
-                       intr_register_source(&pin->io_intsrc);
+               intr_register_source(&pin->io_intsrc);
        }
 }
 
@@ -815,38 +773,8 @@
        program_logical_dest = 1;
        STAILQ_FOREACH(io, &ioapic_list, io_next)
            for (i = 0; i < io->io_numintr; i++)
-                   if (io->io_pins[i].io_dest != DEST_NONE &&
-                       io->io_pins[i].io_dest != DEST_EXTINT)
+                   if (io->io_pins[i].io_dest != DEST_NONE)
                            ioapic_program_destination(&io->io_pins[i]);
 }
 SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
     ioapic_set_logical_destinations, NULL)
-
-/*
- * Support for mixed-mode interrupt sources.  These sources route an ISA
- * IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
- * routes the ISA interrupts.  We just ignore the intpins that use this
- * mode and allow the atpic driver to register its interrupt source for
- * that IRQ instead.
- */
-
-static void
-ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
-{
-       struct ioapic_intsrc *extint;
-       struct ioapic *io;
-
-       /*
-        * Mark the associated I/O APIC intpin as being delivered via
-        * ExtINT and enable the ExtINT pin on the I/O APIC if needed.
-        */
-       intpin->io_dest = DEST_EXTINT;
-       io = (struct ioapic *)intpin->io_intsrc.is_pic;
-       extint = &io->io_pins[0];
-       if (extint->io_vector != VECTOR_EXTINT)
-               panic("Can't find ExtINT pin to route through!");
-#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
-       if (extint->io_dest == DEST_NONE)
-               ioapic_assign_cluster(extint);
-#endif
-}

==== //depot/projects/hammer/sys/amd64/amd64/local_apic.c#48 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/machdep.c#123 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#89 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/mptable.c#40 (text+ko) ====

@@ -348,7 +348,6 @@
                busses[i].bus_type = NOBUS;
 
        /* Second, we run through adding I/O APIC's and busses. */
-       ioapic_enable_mixed_mode();
        mptable_parse_apics_and_busses();       
 
        /* Third, we run through the table tweaking interrupt sources. */

==== //depot/projects/hammer/sys/amd64/amd64/sys_machdep.c#20 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/trap.c#57 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#69 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/conf/NOTES#62 (text+ko) ====

@@ -4,7 +4,7 @@
 # This file contains machine dependent kernel configuration notes.  For
 # machine independent notes, look in /sys/conf/NOTES.
 #
-# (XXX from i386:NOTES,v 1.1191)
+# (XXX from i386:NOTES,v 1.1193)
 # $FreeBSD: src/sys/amd64/conf/NOTES,v 1.28 2005/04/08 20:24:45 obrien Exp $
 #
 
@@ -24,19 +24,10 @@
 #
 # Notes:
 #
-# By default, mixed mode is used to route IRQ0 from the AT timer via
-# the 8259A master PIC through the ExtINT pin on the first I/O APIC.
-# This can be disabled via the NO_MIXED_MODE option.  In that case,
-# IRQ0 will be routed via an intpin on the first I/O APIC.  Not all
-# motherboards hook IRQ0 up to the first I/O APIC even though their
-# MP table or MADT may claim to do so.  That is why mixed mode is
-# enabled by default.
-#
 
 # Optional:
 device         atpic                   # Optional legacy pic support
 device         mptable                 # Optional MPSPEC mptable support
-options        NO_MIXED_MODE           # Disable use of mixed mode
 
 #
 # Watchdog routines.

==== //depot/projects/hammer/sys/amd64/include/apicvar.h#31 (text+ko) ====

@@ -177,7 +177,6 @@
 void   apic_register_enumerator(struct apic_enumerator *enumerator);
 void   *ioapic_create(uintptr_t addr, int32_t id, int intbase);
 int    ioapic_disable_pin(void *cookie, u_int pin);
-void   ioapic_enable_mixed_mode(void);
 int    ioapic_get_vector(void *cookie, u_int pin);
 int    ioapic_next_logical_cluster(void);
 void   ioapic_register(void *cookie);

==== //depot/projects/hammer/sys/amd64/include/clock.h#16 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/include/pc/display.h#6 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/include/pcb.h#22 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/include/pcpu.h#23 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/include/segments.h#19 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/include/sysarch.h#17 (text+ko) ====


==== //depot/projects/hammer/sys/amd64/isa/clock.c#38 (text+ko) ====

@@ -102,6 +102,8 @@
 int    timer0_max_count;
 int    wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
 struct mtx clock_lock;
+#define        RTC_LOCK        mtx_lock_spin(&clock_lock)
+#define        RTC_UNLOCK      mtx_unlock_spin(&clock_lock)
 
 static int     beeping = 0;
 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
@@ -401,30 +403,28 @@
 rtcin(reg)
        int reg;
 {
-       int s;
        u_char val;
 
-       s = splhigh();
+       RTC_LOCK;
        outb(IO_RTC, reg);
        inb(0x84);
        val = inb(IO_RTC + 1);
        inb(0x84);
-       splx(s);
+       RTC_UNLOCK;
        return (val);
 }
 
 static __inline void
 writertc(u_char reg, u_char val)
 {
-       int s;
 
-       s = splhigh();
+       RTC_LOCK;
        inb(0x84);
        outb(IO_RTC, reg);
        inb(0x84);
        outb(IO_RTC + 1, val);
        inb(0x84);              /* XXX work around wrong order in rtcin() */
-       splx(s);
+       RTC_UNLOCK;
 }
 
 static __inline int
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