> I see your point. But I'm not sure such devices can work reliably
> with a write-back cache if regions are not cacheline-aligned.
> For example, I'm almost sure an uchi/ehci can't work reliably on hosts
> with write-back caches (unless the descriptors are mappped uncached).
> I suspect re(4) has the same issue with re_desc->re_cmdstat (the updated
> re_cmdstat from a descriptor may be lost if the host writes another
> descriptor in the same cache line).
Yes, ideally we can allocate only one descriptor per each cacheline
to avoid race, but not all devices (for PC) assume such hardware.
In such case, BUS_DMA_COHERENT is mandatory.
But anyway we can't invalidate cache in POSTREAD/POSTWRITE
because they have the same problems even on data xfers.