David Daney wrote:
> > gcc/ChangeLog
> > 2009-10-05 Chao-ying Fu <fu@xxxxxxxx>
> > * config/mips/mips.c (mips_expand_synci_loop):
> Increment the "begin" rtx,
> > then check the "begin" rtx against the "end" rtx.
> I cannot approve the patch, but it seems plausible.
> Can you tell us how it was tested?
Actually, I just built the whole GCC mainline again.
This bug was detected on Debian on a 24kf Malta board, when I was
doing a JIT application that needs to flush cache for some generated MIPS code.
I found that my patch may skip the last synci for the end address (-1).
Maybe we need to append an extra synci at the end.
Ex: (New code)
46c724: rdhwr v1,hwr_synci_step
46c728: synci 0(a1)
46c72c: addu a1,a1,v1
46c730: sltu v0,a2,a1
46c734: beqz v0,46c728
46c73c: addiu a2,a2,-1
46c740: synci 0(a2)
I am still thinking about how to improve this sequence. If anyone has a
please let me know. Thanks!