[Patch] MIPS: three V2SF RTL patterns

["Chao-ying Fu"]

  This patch adds three V2SF RTL patterns: vcondv2sf, sminv2sf3, smaxv2sf3
that
can be used by the auto-vectorizer.  Tested for mipsisa64-elf and one
unexpected failure is fixed by this patch.

PASS: gcc.dg/vect/fast-math-vect-reduc-5.c scan-tree-dump-times vectorized 3
loops 1

  Would the patch be ok?  Thanks a lot!

Regards,
Chao-ying

2005-11-01  Chao-ying Fu  <fu@xxxxxxxx>

    * config/mips/mips-ps-3d.md (vcondv2sf, sminv2sf3, smaxv2sf3): New
    patterns.
    * config/mips/mips/protos.h: Declare mips_expand_fp_vcond and
    mips_expand_fp_vector_minmax.
    * config/mips/mips.c (mips_expand_fp_vcond,
    misp_expand_fp_vector_minmax): New functions.

Index: mips-ps-3d.md
===================================================================
--- mips-ps-3d.md (revision 106337)
+++ mips-ps-3d.md (working copy)
@@ -475,3 +475,39 @@
   "recip2.<fmt>\t%0,%1,%2"
   [(set_attr "type" "frdiv2")
    (set_attr "mode" "<UNITMODE>")])
+
+(define_expand "vcondv2sf"
+  [(set (match_operand:V2SF 0 "register_operand" "")
+ (if_then_else:V2SF
+   (match_operator 3 ""
+     [(match_operand:V2SF 4 "register_operand" "")
+      (match_operand:V2SF 5 "register_operand" "")])
+   (match_operand:V2SF 1 "register_operand" "")
+   (match_operand:V2SF 2 "register_operand" "")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  if (mips_expand_fp_vcond (operands))
+    DONE;
+  else
+    FAIL;
+})
+
+(define_expand "sminv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "")
+ (smin:V2SF (match_operand:V2SF 1 "register_operand" "")
+     (match_operand:V2SF 2 "register_operand" "")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  mips_expand_fp_vector_minmax (0, operands);
+  DONE;
+})
+
+(define_expand "smaxv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "")
+ (smax:V2SF (match_operand:V2SF 1 "register_operand" "")
+     (match_operand:V2SF 2 "register_operand" "")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  mips_expand_fp_vector_minmax (1, operands);
+  DONE;
+})
Index: mips-protos.h
===================================================================
--- mips-protos.h (revision 106337)
+++ mips-protos.h (working copy)
@@ -224,4 +224,7 @@
 extern unsigned int current_section_flags (void);
 extern bool mips_use_ins_ext_p (rtx, rtx, rtx);

+extern bool mips_expand_fp_vcond (rtx[]);
+extern bool mips_expand_fp_vector_minmax (int, rtx[]);
+
 #endif /* ! GCC_MIPS_PROTOS_H */
Index: mips.c
===================================================================
--- mips.c (revision 106337)
+++ mips.c (working copy)
@@ -10745,6 +10745,116 @@

   return target;
 }
+
+/* Expand floating-ponit vector conditional move pattern.  */
+
+bool mips_expand_fp_vcond (rtx operands[])
+{
+  rtx cmp_result, op1, op2, op4, op5;
+  enum rtx_code code = GET_CODE (operands[3]);
+  bool swap_cmp = false;
+  bool swap_movtf = false;
+  int cond;
+
+  if (code == NE || code == LTGT || code == ORDERED)
+    {
+      code = reverse_condition_maybe_unordered (code);
+      swap_movtf = true;
+    }
+
+  /* Map code to cond */
+  switch (code)
+  {
+  case UNORDERED:
+    cond = MIPS_FP_COND_un;
+    break;
+  case UNEQ:
+    cond = MIPS_FP_COND_ueq;
+    break;
+  case UNLT:
+    cond = MIPS_FP_COND_ult;
+    break;
+  case UNLE:
+    cond = MIPS_FP_COND_ule;
+    break;
+  case EQ:
+    cond = MIPS_FP_COND_eq;
+    break;
+  case LT:
+    cond = MIPS_FP_COND_lt;
+    break;
+  case LE:
+    cond = MIPS_FP_COND_le;
+    break;
+  case GE:
+    swap_cmp = true;
+    cond = MIPS_FP_COND_le;
+    break;
+  case GT:
+    swap_cmp = true;
+    cond = MIPS_FP_COND_lt;
+    break;
+  case UNGE:
+    swap_cmp = true;
+    cond = MIPS_FP_COND_ule;
+    break;
+  case UNGT:
+    swap_cmp = true;
+    cond = MIPS_FP_COND_ult;
+    break;
+  default:
+    return false;
+  }
+
+  cmp_result = gen_reg_rtx (CCV2mode);
+  if (swap_cmp == false)
+    {
+      op4 = operands[4];
+      op5 = operands[5];
+    }
+  else
+    {
+      op4 = operands[5];
+      op5 = operands[4];
+    }
+  if (swap_movtf == false)
+    {
+      op1 = operands[1];
+      op2 = operands[2];
+    }
+  else
+    {
+      op1 = operands[2];
+      op2 = operands[1];
+    }
+  emit_insn (gen_mips_c_cond_ps (cmp_result, op4, op5, GEN_INT (cond)));
+  emit_insn (gen_mips_cond_move_tf_ps (operands[0], op1, op2, cmp_result));
+  return true;
+}
+
+/* Expand floating-ponit vector smin/smax patterns.
+   minmax is 0 for the smin pattern, and 1 for the smax pattern.  */
+
+bool mips_expand_fp_vector_minmax (int minmax, rtx operands[])
+{
+  rtx op1, op2;
+  int cond = MIPS_FP_COND_le;
+  rtx cmp_result = gen_reg_rtx (CCV2mode);
+  if (minmax == 0)
+    {
+      op1 = operands[1];
+      op2 = operands[2];
+    }
+  else
+    {
+      op1 = operands[2];
+      op2 = operands[1];
+    }
+  emit_insn (gen_mips_c_cond_ps (cmp_result, op1, op2, GEN_INT (cond)));
+  emit_insn (gen_mips_cond_move_tf_ps (operands[0], operands[1],
operands[2],
+           cmp_result));
+  return true;
+}
 
 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to
DECL.
    FIRST is true if this is the first time handling this decl.  */