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jacob navia wrote, On 27/03/08 17:09:
Flash Gordon wrote:
jacob navia wrote, On 27/03/08 15:37:
Ed Prochak wrote:
Harvard Architecture is one in which code address space and data
address space are totally separate, not merely "non linear".
The EPROM is in a totally different bus, but you can put
as well code or data in both parts of memory.
Whether it is EPROM, ROM or RAM is irrelevant. In a Harvard
Architecture code and data are separate address address spaces.
The wiki says:
Harvard architectures are also frequently used in:
The wiki correctly refers to separate pathways for code and data, you
did not read it correctly.
I CAN read.
You don't seem to have understood so perhaps you did not actually read
but just assumed it said what you expected.
EPROM is normally used for code, and RAM for
data. But that distinction is blurred if you store
constant data in EPROM,
On a Harvard Architecture it isn't blurred at all, because you cannot do
data reads from the instruction space.
for instance (as I said)
constant character strings or tables, whatever.
Won't do you much good if you cannot read it because it is in the
instruction space and only instructions can be read from the instruction
space. That is the situation with a Harvard Architecture. Therefore you
statement quoted at the top of this post is completely wrong.
This is also used in other processors when character
strings are stored with the code...
Which you cannot do in a Harvard Architecture because there would be no
way to read it. The nearest you could do is something like
LD A,'H'
ST IDX,A
INC IDX
LD A,'e'
ST IDX,A
INC IDX
...
Rather painful you can see. However, since on a Harvard Architecture the
only thing it is physically possible to read from the instruction space
is instructions to be executed the only way to get data out of it is an
instruction that has the data embedded in it.
This is why Texas Instruments use a Modified Harvard Architecture, and I
suspect that what you are thinking about is the Modified Harvard
Architecture. The Modified Harvard Architecture does allow you to read
data from the instruction space.
Oh, and if you read the documentation for the referenced Analog Devices
processor it says:
• A multi-issue load/store modified Harvard architecture, which sup-
^^^^^^^^
ports two 16-bit MAC or four 8-bit ALU + two load/store + two
pointer updates per cycle
This is in
http://www.analog.com/UploadedFiles/Associated_Docs/34116712859348BF52xProcHWR03.pdf
Page 1-26.
Therefore Wikipedia is wrong again. I've deleted that example stating
that it is wrong.
--
Flash Gordon
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